The present invention is related in general to the field of semiconductor devices and processes, and more specifically to encapsulation methods for integrated circuit chips resulting in thin and substantially flat packages having substantially the same outline as the circuit chip.
During the last few years, a major trend in the semiconductor industry has been the effort to shrink semiconductor packages so that the package outline consumes less area and less height when it is mounted onto customer circuit boards, and to reach these goals with minimum cost (both material and manufacturing cost). One of the most successful approaches has been the development of so-called xe2x80x9cchip-scale packagesxe2x80x9d. These packages have an outline adding less than 20% to the chip area. A chip-scale package which has only the outline of the chip itself, is often referred to as xe2x80x9cchip-size packagexe2x80x9d. While a number of designs have been successfully demonstrated to achieve substantially flat packages having substantially the same outline as the circuit chip, the reduction in device thickness has been quite limited and essentially elusive.
One of the earliest successful approaches to chip-scale packaging includes the use of sheet-like polymer interposers between and/or around elements of the semiconductor packages in order to reduce and/or redistribute the strain and stress on the connections between the semiconductor chip and the supporting circuitized substrate during operation of the chip. A description can be found for instance in U.S. Pat. No. 5,148,266, Sep. 15, 1992 (Khandros et al.) entitled xe2x80x9cSemiconductor Chip Assemblies having Interposer and Flexible Leadxe2x80x9d. It introduces a spacer layer (made of compliant or elastomeric material) between a top surface of a sheet-like substance and a contact bearing surface of a semiconductor chip, wherein the substrate has conductive leads thereon, the leads being electrically connected to terminals on a first end and bonded to respective chip contacts to a second end.
In U.S. Pat. No. 5,776,796, Jul. 7, 1998 (Distefano et al.) entitled xe2x80x9cMethod of Encapsulating a Semiconductor Packagexe2x80x9d, the encapsulation method introduces curable liquids such as electronic grade silicone-based.or epoxy-based resins by using needle-like dispensers, moving around the periphery of the chip, until the desired level of encapsulant has been substantially uniformly dispensed. Dependent on the material, the encapsulant is then cured by radiant energy, thermal energy, moisture, or ultraviolet light. Typically, this encapsulation method is performed simultaneously on a plurality of chips which are sharing a common frame. Finally, a dicing saw, water jet, ultrasonic knife, rotary razor, or laser separates the encapsulated chip assembly structure from the frame so that the resultant chip package is no, or only slightly, wider than the periphery of the chip itself. With some effort, the encapsulate will not flow onto the back surface of the chip; it can thus subsequently be connected to a heat sink without an insulative material impeding the dissipation of heat from the chip.
Within the semiconductor memory product families, one of the most promising concepts for chip-scale packages is the so-called xe2x80x9cboard-on-chipxe2x80x9d design. Recently, patent application entitled xe2x80x9cChip-size Integrated Circuit Packagexe2x80x9d has been filed by Texas Instruments in Singapore on Jul. 02, 1997 under Ser. No. 9702348-5, and in the USA on Dec, 19, 1997 under Ser. No. 08/994,627. An approach to reduce the package height and to reach a low device profile with the board-on-chip design has been described in the patent applications entitled xe2x80x9cThin Chip-size Integrated Circuit Package and Method of Fabricationxe2x80x9d filed in Singapore on Jan. 2, 1998 under Ser. Nos. 9,800,005-2 and 9,800,006-0. These devices use wire ball bonding for assembly; because of the extreme sensitivity of the thin wires against mechanical disturbances, careful protection by reliable encapsulation is needed; liquid potting material is dispensed by needle-like syringes and later cured. If solder balls are used to assemble the devices on circuit boards, this encapsulation has to withstand the mechanical stress caused by the difference in thermal expansion coefficients of the material involved.
Since in all these approaches to chip-scale packages, the process of encapsulating the device comprises distributing semi-viscous material from the openings of syringes onto preselected regions of the device surfaces to be covered, and then distributing the material over the whole area and into openings to be filled with the help of capillary forces, this technology obviously suffers from-several shortcomings. Foremost, the existing technology is not economical. In order to keep the number of dispensers in practical limits, only a modest number of packages can be encapsulated in one fabrication step; the process does not lend itself to mass production. Secondly, the process is hard to control uniformly, and prone to statistical variations such as uneven fillings, pronounced meniscus formation, or flaws such as voids. It has been the experience over several years of production that a high percentage of the devices exhibit cosmetic flows. Further, the choice of materials is limited to liquid materials which typically require prolonged xe2x80x9ccuringxe2x80x9d times for polymerization and hardening, causing high mechanical stress in the product. In addition, the liquids tend to splatter onto exposed semiconductor surfaces, thus causing particulate contamination inhibiting the application of flat heat sinks.
Understandably, efforts have been expanded to apply the conventional transfer molding technology to produce thin semiconductor products. The transfer molding technology was introduced to semiconductor devices (U.S. Pat. Nos. 3,716,764 and 4,043,027) as an encapsulation process which is both gentle and reliable, and exceedingly well applicable to mass production. Over the years, transfer molding has been applied to almost all semiconductor device types, but it has proved extraordinarily difficult to produce devices thinner than about 0.8 mm total thickness. The main difficulty has been the adhesion of the molding material to the cavity walls of the steel molds, which proved to become dominant over the adhesion of the molding material to the device parts when the molded layers shrink below about 0.2 mm thickness (dependent on the chemistry of the material). The thin molded layers also tended to break after polymerization.
A partial solution arrived with U.S. Pat. No. 5,098,626 of Mar. 24, 1992 (Pas, xe2x80x9cMethod for Packing a Measured Quantity of Thermosetting Resin and Operating a Mold for Encapsulating a Componentxe2x80x9d) and U.S. Pat. No. 5,431,854 of Jul. 11, 1995 (Pas, xe2x80x9cMethod for Pressing a Plastic, which Cures by means of a Reaction, into a Mold Cavity, a Pressing Auxiliary in Pill Form to be Used in this Method, and a Holder Composed of such Materialxe2x80x9d). The emphasis is placed on cleanliness of the molding material by prepacking and sealing it in plastic forms which are only ruptured at time of usage, and on preventing the deleterious adhesion to the mold cavity walls of the molding material by covering thin continuous plastic films over-the mold walls. For this purpose, the pulling forces from vacuum xe2x80x9cdispensedxe2x80x9d from numerous openings pressure the flexible films against the walls, thus keeping the molding material away from the walls. However, until now the so-called xe2x80x9c3-Pxe2x80x9d technology is intended for encapsulating only standard-size semiconductor devices and does not offer the unique processes, mold designs or molding materials needed for encapsulating devices with at least one minimized geometry.
An urgent need has therefore arisen for a coherent, low-cost method of encapsulating thin semiconductor chip-scale packages. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, should eliminate all cosmetic and substantial flaws in those products, and should allow the usage of various formulations of encapsulating materials. Preferably, these innovations should be accomplished while shortening production cycle time and increasing throughput.
The present invention provides a method of encapsulating a semiconductor device; it especially relates to high density integrated circuits in packages which have an outline similar to the integrated circuit chip itself, and a low profile. These circuits can be found in many device families such as processors, digital and analog devices, memory and logic devices, high frequency and high power devices, especially in large chip area categories. The invention helps to alleviate the space constraint of continually shrinking applications such as cellular communications, pagers, hard disk drives, laptop computers and medical instrmentation.
In accordance with the present invention, a molding method and apparatus are provided in conjunction with specially developed encapsulation materials of low viscosity and high adhesion The.transfer molding process based on the invention results in ultra-thin devices free of any voids and having unusually flat surfaces and high luster. The combination of system and special materials for the transfer molding process further allows an order of magnitude higher production throughput compared to conventional potting encapsulation. The method comprises the option of retaining one chip surface free from any contamination, or to overmold it with a protective layer of predetermined thickness.
It is an object of the present invention to be applicable to a variety of different semiconductor chip-scale package (CSP) designs, for example: Active chip surface assembled on connection-carrying interposer, passive chip surface assembled on connection-carrying interposer, board-on-chip assembly, peripheral bonding, center-line bonding, area bonding, wire bonding and flip-chip.
For the miniaturized assembly feature sizes to be encapsulated free of voids, the invention replaces the conventional potting method by a transfer molding technique. Low viscosity of the encapsulation material is required. In order to achieve the desired low profile on the order of 0.5 mm, strong adhesion of the encapsulation material to all differentiated materials of the assembly is required. The invention solves these conflicting needs by developing new encapsulation material formulations and processing these materials in a modified xe2x80x9c3-Pxe2x80x9d molding technique with its film-protected mold surfaces.
As side benefits of using the xe2x80x9c3-Pxe2x80x9d technology, the pre-assembled devices are protected against contamination and chip cracking, and the mold system avoids down time and cost due to customary routine cleaning requirements.
It is an object of the present invention to provide a low-cost method and system for packaging chip-scale devices in thin overall profile.
Another object of the present invention is to provide a significantly higher production throughput.
Another object of the invention is to improve product quality by eliminating cosmetic flaws and obtaining precise and reproducible geometries for the finished product, and to provide reliability assurance through in-process control at no extra cost.
Another object of the invention is to introduce assembly concepts for thin profiles and reliability which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several future generations of products.
Another object of the invention is to minimize the cost of capital investment and the movement of parts and product in the equipment.
These objects have been achieved by the teachings of the invention concerning systems and methods suitable for mass production. Various modifications have been employed for the encapsulation of assembled semiconductor chips as well as connective interposers and substrates.
In one embodiment of the invention, the encapsulation material is pressured into the mold cavity when the gate is located above the plane defined by the interposer (socalled xe2x80x9ctop gatexe2x80x9d arrangement).
In another embodiment of the invention, the encapsulation material is pressured into the mold cavity when the gate is located below the plane defined by the interposer (so-called xe2x80x9cbottom gatexe2x80x9d arrangement).
In another embodiment of the invention, the ranges and combinations of viscosity, glass transition temperature, and filler size of the encapsulation material are modified and varied in order to optimize the flow characteristics and adhesion of the material as a function of the molding system parameters.
In another embodiment of the invention, the apparatus for the transfer molding in the fabrication of a semiconductor device comprises pairs of runners with a plurality of dual gates supplying encapsulation material simultaneously and uniformly for forming ultra-thin chip-scale packages.
In another embodiment of the invention, the molding process parameters (temperature, time, pressure, transfer, curing, etc.) are modified in order to optimize them relative to the system and process parameters.
In yet another aspect of the invention, benefits are derived from the fast-speed singulation methods (such as sawing) of the encapsulated devices, and the lower costs of the molding compounds and methods (as compared to potting materials and methods).
The technical advances represented by the invention, as well as the objects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.